中圖分類號：TP311.5 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.245035 中文引用格式： 沈煒，劉詩宇，楊光，等. 面向密碼芯片設計階段的仿真側信道安全性分析方法研究[J]. 電子技術應用，2024，50(10)：98-104. 英文引用格式： Shen Wei，Liu Shiyu，Yang Guang，et al. Research on side channel security analysis technology of cryptographic chip based on simulation[J]. Application of Electronic Technique，2024，50(10)：98-104.
Research on side channel security analysis technology of cryptographic chip based on simulation
Shen Wei，Liu Shiyu，Yang Guang，Li Dongfang
Institute 706， Second Academy of CASIC
Abstract： Cryptographic chip is an important carrier for cryptographic algorithms, which implements functions such as encryption, decryption, signature, and authentication of information system. Side channel analysis is an important method to verify the security of cryptographic chips. In the current industry, post-silicon side channel analysis with special equipment is a common method, which is too late and expensive in making any changes to the design to solve the leakage issue. This paper proposes a simulation-based power trace acquisition and side channel analysis method. EDA tools are used to perform functional simulation on the RTL code of the cryptographic chip during the design phase, and we collect the simulated power trace by analyzing the waveform record file. By using Welch t test, KL divergence and correlation energy analysis, leakage can be located in time and space dimensions. Through the side channel analysis experiment on AES-128 RTL design, we proved that the method proposed in this paper can correctly reflect the power leakage, which can detect the side channel leakage risk in the early stage of the cryptographic chip design without the help of special hardware equipment.
Key words : cryptographic chip；power consumption simulation；leakage detection；power side channel attack
