基于自動(dòng)編譯碼器的端到端無(wú)線通信系統(tǒng)FPGA實(shí)現(xiàn)
2023年電子技術(shù)應(yīng)用第5期
黃沛昱，高磊，宋佳波
（重慶郵電大學(xué) 光電工程學(xué)院，重慶 400065）
摘要： 基于自動(dòng)編譯碼器的通信系統(tǒng)是近年來(lái)無(wú)線通信的一個(gè)熱門(mén)研究領(lǐng)域，如何將其部署在嵌入式設(shè)備中具有非常重要的實(shí)踐意義。提出了一種基于自動(dòng)編譯碼器的端到端無(wú)線通信系統(tǒng)的FPGA設(shè)計(jì)方案，在FPGA上部署基于自動(dòng)編譯碼器的端到端無(wú)線通信系統(tǒng)，使用AD9361射頻芯片作為射頻前端處理模塊，實(shí)現(xiàn)真正意義上的空中傳輸。并且對(duì)系統(tǒng)中的卷積神經(jīng)網(wǎng)絡(luò)設(shè)計(jì)了硬件加速方案，在卷積計(jì)算單元內(nèi)進(jìn)行并行性探索，設(shè)計(jì)了流水線架構(gòu)，加速卷積運(yùn)算。對(duì)于存儲(chǔ)單元，采用雙緩沖設(shè)計(jì)，利用乒乓操作，提高數(shù)據(jù)通信速率。實(shí)驗(yàn)結(jié)果表明，在不同的調(diào)制方式下，系統(tǒng)實(shí)測(cè)誤塊率與在瑞利信道下的仿真結(jié)果相接近。在誤塊率相當(dāng)?shù)那闆r下，與通用CPU Intel i5-9300相比，所設(shè)計(jì)的系統(tǒng)的網(wǎng)絡(luò)推理速度提升了3.98倍。與英偉達(dá)1650 GPU相比，功耗約是它的0.18倍。
中圖分類號(hào)：TN92
文獻(xiàn)標(biāo)志碼：A
DOI: 10.16157/j.issn.0258-7998.223229
中文引用格式： 黃沛昱，高磊，宋佳波. 基于自動(dòng)編譯碼器的端到端無(wú)線通信系統(tǒng)FPGA實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用，2023，49(5)：105-110.
英文引用格式： Huang Peiyu，Gao Lei，Song Jiabo. FPGA implementation of end-to-end wireless communication system based on auto-encoder[J]. Application of Electronic Technique，2023，49(5)：105-110.
文獻(xiàn)標(biāo)志碼：A
DOI: 10.16157/j.issn.0258-7998.223229
中文引用格式： 黃沛昱，高磊，宋佳波. 基于自動(dòng)編譯碼器的端到端無(wú)線通信系統(tǒng)FPGA實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用，2023，49(5)：105-110.
英文引用格式： Huang Peiyu，Gao Lei，Song Jiabo. FPGA implementation of end-to-end wireless communication system based on auto-encoder[J]. Application of Electronic Technique，2023，49(5)：105-110.
FPGA implementation of end-to-end wireless communication system based on auto-encoder
Huang Peiyu，Gao Lei，Song Jiabo
(School of Opto-electronic Engineering， Chongqing University of Posts and Telecommunications， Chongqing 400065， China)
Abstract： The communication system based on auto-encoder is a hot research field of communication system in recent years, and how to apply the end-to-end learning communication systems to embedded devices is a hot topic worthy of research. This paper proposes a FPGA design scheme for end-to-end wireless communication system based on auto-encoder, deploys the end-to-end wireless communication system based on auto-encoder on the FPGA, and uses the AD9361 radio frequency chip as the radio frequency front-end processing module to achieve real air transmission. In addition, a hardware acceleration scheme is designed for the CNN in the system, parallelism is explored in the convolution computing unit, and a pipeline architecture is designed to accelerate the convolution operation. For the storage unit, the double buffer design is adopted, and the ping-pong operation is used to improve the utilization rate of data communication bandwidth. The experimental results show that under different modulation methods, the BLER performance is close to the simulation results under the Rayleigh fading channel. Compared with the general-purpose CPU i5-9300, the network inference speed of the designed system is 3.98 times higher than that of the general-purpose CPU i5-9300 with the same block error rate. Compared to the Nvidia 1650 GPU, the power is about 0.18 times higher.
Key words : FPGA；auto-encoder；end to end communication；pipeline；AD9361
0 引言
對(duì)于一個(gè)完整的通信系統(tǒng)來(lái)說(shuō)，其本質(zhì)可以表示為發(fā)射端為所需要發(fā)送的信息設(shè)計(jì)一種合適的編碼方式，以便于在傳輸過(guò)程中即使遇到各種外界干擾，也能將信息從發(fā)射端準(zhǔn)確安全地傳輸?shù)浇邮斩恕鹘y(tǒng)的通信系統(tǒng)通過(guò)將發(fā)射端和接收端設(shè)計(jì)為若干個(gè)子模塊，如信源編碼、調(diào)制、解調(diào)、信道解碼、信道均衡等，通過(guò)對(duì)系統(tǒng)中的每個(gè)模塊進(jìn)行單獨(dú)優(yōu)化保證通信質(zhì)量。但傳統(tǒng)通信系統(tǒng)實(shí)現(xiàn)的是局部?jī)?yōu)化，無(wú)法對(duì)系統(tǒng)進(jìn)行全局最優(yōu)設(shè)計(jì)。
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作者信息：
黃沛昱，高磊，宋佳波
（重慶郵電大學(xué) 光電工程學(xué)院，重慶 400065）
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