中圖分類號： TN911.22 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.201025 中文引用格式： 張健，吳倩文，高澤峰，等. 卷積編碼及Viterbi譯碼的低時延FPGA設(shè)計實現(xiàn)[J].電子技術(shù)應(yīng)用，2021，47(6)：96-99. 英文引用格式： Zhang Jian，Wu Qianwen，Gao Zefeng，et al. Low-latency FPGA design and implementation of convolutional coding and Viterbi decoding[J]. Application of Electronic Technique，2021，47(6)：96-99.
Low-latency FPGA design and implementation of convolutional coding and Viterbi decoding
Zhang Jian，Wu Qianwen，Gao Zefeng，Zhou Zhigang
School of Electronic Information，Hangzhou Dianzi University，Hangzhou 310018，China
Abstract： Aiming at the high-speed and low-delay design requirements of millimeter wave communications, this paper designs low-delay decoding of convolutional codes with 1/2 code rate(2，1，7). A highly parallel optimization implementation framework and a low-latency minimum selection method are adopted to obtain the output of the Viterbi hard decision decoding algorithm. After synthesis using the Artix7-xc7a200t chip based on Xilinx, the data output delay of the decoder is about 89 clock cycles, and the highest operating frequency can reach 203.92 MHz. The results show that the decoder can support gigabit-level data transmission rates, and realizes a low-latency, high-rate codec.
Key words : millimeter wave communication；convolutional code；Viterbi decoding；system generator
