AD9547是雙路/四路輸入網(wǎng)絡(luò)時鐘發(fā)生器/同步器,能為許多系統(tǒng)包括同步光網(wǎng)絡(luò)(SONET/SDH)提供同步.輸入基準(zhǔn)頻率從1 kHz 到750 MHz,頻率監(jiān)視1ppm,輸出頻率高達(dá)450MHz,主要應(yīng)用在網(wǎng)絡(luò)同步,OC-192的SONET/SDH時鐘,無線基站,控制器,有線基礎(chǔ)設(shè)備和數(shù)據(jù)通信. 本文介紹了AD9547主要特性, 功能方框圖,詳細(xì)方框圖, 輸出同步方框圖和評估板電路圖以及評估板材料清單.

AD9547: Dual/Quad Input Network Clock Generator/Synchronizer

The AD9547 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9547 continuously generates a clean (low jitter), valid output clock, even when all references fail, by means of digitally controlled loop and holdover circuitry. The AD9547 operates over an industrial temperature range of −40℃ to +85℃.

AD9547主要特性:

Supports Stratum 2 stability in holdover mode

Supports reference switchover with phase build-out

Supports hitless reference switchover

Automatic/manual holdover and reference switchover

2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent single-ended inputs

Input reference frequencies from 1 kHz to 750 MHz

Reference validation and frequency monitoring (1 ppm)

Programmable input reference switchover priority

30-bit programmable input reference divider

2 pairs of clock output pins, with each pair configurable as a single differential LVDS/LVPECL output or as 2 single-ended CMOS outputs

Output frequencies up to 450 MHz

20-bit integer and 10-bit fractional programmable feedback divider

Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz

Optional low noise LC-VCO system clock multiplier

Optional crystal resonator for system clock input

On-chip EEPROM to store multiple power-up profiles

Software controlled power-down

64-lead LFCSP package

AD9547應(yīng)用:

Network synchronization

Cleanup of reference clock jitter

SONET/SDH clocks up to OC-192, including FEC

Stratum 2 holdover, jitter cleanup, and phase transient control

Stratum 3E and Stratum 3 reference clocks

Wireless base stations, controllers

Cable infrastructure

Data communications

 圖1.AD9547功能方框圖

圖2.AD9547詳細(xì)方框圖

圖3.AD9547輸出同步方框圖

圖4.AD9547評估板電路圖(1)


圖5.AD9547評估板電路圖(2)


圖6.AD9547評估板電路圖(3)