探索分布式仿真方法加速Chiplet系統(tǒng)級驗(yàn)證
電子技術(shù)應(yīng)用
徐加山1，何金鑫1，劉紅云1，徐志磊2
1.深圳市中興微電子技術(shù)有限公司；2.上?？请娮涌萍加邢薰?/div>
摘要： 隨著人工智能（AI）和高性能計(jì)算領(lǐng)域?qū)π酒懔π枨蟮脑鲩L，Chiplet方案正日益受到行業(yè)重視。然而Multi-Die系統(tǒng)復(fù)雜性和規(guī)模的擴(kuò)大導(dǎo)致仿真消耗服務(wù)器資源大、驗(yàn)證交付周期延長等。為解決這些問題，分析了傳統(tǒng)的三步法和Socket驗(yàn)證方法，重點(diǎn)探索了Cadence分布式仿真方案，基于某實(shí)際Chiplet項(xiàng)目將系統(tǒng)級仿真任務(wù)分解成多個(gè)子Die并行執(zhí)行的仿真實(shí)例，從服務(wù)器內(nèi)存、跨服務(wù)器通信延遲、同步時(shí)間精準(zhǔn)調(diào)控、信號連接開始時(shí)間及信號連接數(shù)量等多個(gè)方面探索了分布式仿真提效的措施，實(shí)現(xiàn)了超大規(guī)模Chiplet系統(tǒng)級RTL仿真和回歸效率提升。
中圖分類號：TN407 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.250807
中文引用格式： 徐加山，何金鑫，劉紅云，等. 探索分布式仿真方法加速Chiplet系統(tǒng)級驗(yàn)證[J]. 電子技術(shù)應(yīng)用，2025，51(8)：35-39.
英文引用格式： Xu Jiashan，He Jinxin，Liu Hongyun，et al. Research on accelerating chiplet system level verification with distributed simulation technology[J]. Application of Electronic Technique，2025，51(8)：35-39.
中文引用格式： 徐加山，何金鑫，劉紅云，等. 探索分布式仿真方法加速Chiplet系統(tǒng)級驗(yàn)證[J]. 電子技術(shù)應(yīng)用，2025，51(8)：35-39.
英文引用格式： Xu Jiashan，He Jinxin，Liu Hongyun，et al. Research on accelerating chiplet system level verification with distributed simulation technology[J]. Application of Electronic Technique，2025，51(8)：35-39.
Research on accelerating chiplet system level verification with distributed simulation technology
Xu Jiashan1，He Jinxin1，Liu Hongyun1，Xu Zhilei2
1.Sanechips Technology Co.，Ltd.；2.Cadence Design Systems，Inc.
Abstract： With the increasing demand for chip computing power in the fields of AI and high-performance computing, the chiplet solution is attracting more and more attention in the industry. However, the expansion of complexity and scale in multi-Die systems leads to issues such as high server resource consumption during simulation and extended verification delivery cycles. To solve these problems, this paper analyzes the traditional three-step method and socket verification method, and focuses on the Cadence distributed simulation solution. Based on an actual chiplet project, this paper breaks down system-level simulation tasks into multiple sub-Dies for parallel execution, and explores distributed simulation measures to improve efficiency from multiple aspects, such as server memory, cross-server communication delay, precise synchronization time adjustment, signal connection start time, and signal connection quantity. This achieves ultra-large-scale chiplet system-level RTL simulation and improves regression efficiency.
Key words : chiplet；system level validation；distributed simulation technology
引言
隨著高性能計(jì)算、人工智能及自動駕駛等帶寬密集型應(yīng)用的快速發(fā)展，傳統(tǒng)大的單芯片面臨良率風(fēng)險(xiǎn)，推動著系統(tǒng)架構(gòu)正從傳統(tǒng)單芯片向多芯片集成方向演進(jìn)，但這也導(dǎo)致系統(tǒng)級驗(yàn)證難度顯著增加。現(xiàn)有驗(yàn)證方法在應(yīng)對Chiplet系統(tǒng)級仿真時(shí)存在運(yùn)行效率低下、驗(yàn)證交付周期長等問題。因此，本文探索了基于分布式仿真的驗(yàn)證方案，通過構(gòu)建并行化仿真任務(wù)調(diào)度機(jī)制和資源分配策略，實(shí)現(xiàn)多芯片協(xié)同驗(yàn)證的效率提升。
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http://www.shi-ke.cn/resource/share/2000006626
作者信息：
徐加山1，何金鑫1，劉紅云1，徐志磊2
（1.深圳市中興微電子技術(shù)有限公司，江蘇 南京 210012；2.上?？请娮涌萍加邢薰?，上海 200235）
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