中圖分類號： TN492 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.211418 中文引用格式： 張自豪，趙建中，周玉梅. 基于MIPI規范的從端D-PHY數字電路設計[J].電子技術應用，2021，47(11)：33-38. 英文引用格式： Zhang Zihao，Zhao Jianzhong，Zhou Yumei. Design of slave D-PHY digital circuit based on MIPI specification[J]. Application of Electronic Technique，2021，47(11)：33-38.
Design of slave D-PHY digital circuit based on MIPI specification
Zhang Zihao1，2，Zhao Jianzhong1，Zhou Yumei1，2
1.Institute of Microelectronics，Chinese Academy of Science，Beijing 100029，China； 2.University of Chinese Academy of Sciences，Beijing 100049，China
Abstract： Based on the MIPI D-PHY version 1.1 specification, a design of slave D-PHY digital circuit is proposed, which is implemented with 4 lanes. In the high-speed mode, the data transfer rate of a single lane supports up to 1.5 Gb/s; in the low-power mode, the data transfer rate of lane 0 is up to 10 Mb/s. In the high-speed mode, the deserialization of the serial data stream is implemented by the analog circuit, and the synchronization detection of the data frame header after deserialization is realized by the digital circuit; the detection of the D-PHY entry code and the data transmission in the low-power mode are asynchronous communication and a kind of asynchronous clock implementation is proposed; SMIC 0.18 μm CMOS process library is used for synthesis, and at the typical process corner, the overall circuit area is 95 061 μm2; the overall power consumption is 4.291 mW, and the power consumption in low power mode is 231.3 μW.
Key words : MIPI；D-PHY；high speed mode；low-power mode；asynchronous clock
0 引言
早在2003年，ARM、諾基亞、德州儀器和意法半導體四家公司就預見了智能、多媒體手機的廣闊市場前景，成立了移動產業處理器接口(Mobile Industry Processor Interface，MIPI)聯盟[1]。目前，所有主要的芯片廠商使用MIPI規范，所有智能手機都至少使用一種MIPI規范。串行顯示接口(Display Serial Interface，DSI)協議是MIPI聯盟推出的針對高速顯示接口的規范[2]，多用于移動終端系統[3]，其特點是高速、靈活和低功耗[4]。DSI協議架構的最低層是物理層(Physical Layer，PHY)，規范了發送端(主端)和接收端(從端)通道的電學特性和通道建立時的時序要求[5]。D-PHY規范是一種常用的兼容DSI協議的物理層規范[6]。
