中圖分類號： TN405.97
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.211370
中文引用格式： 王夢雅，曾燕萍，張景輝，等. 基于SiP封裝的DDR3時序仿真分析與優(yōu)化[J].電子技術(shù)應用，2021，47(10)：42-47.
英文引用格式： Wang Mengya，Zeng Yanping，Zhang Jinghui，et al. Timing simulation analysis and optimization of DDR3 based on SiP package[J]. Application of Electronic Technique，2021，47(10)：42-47.

Timing simulation analysis and optimization of DDR3 based on SiP package

Abstract： Aiming at the timing requirements of DDR3 system, timing simulation and optimization were carried out for DDR3 package and substrate design in a SiP(System in Package). Through simulation guidance design, the design success rate of DDR3 in SiP product was improved and the design cycle was reduced. The signal scattering parameters were extracted by ANSYS SIwave software, and then the topology construction and timing simulation analysis was carried out through Cadence SystemSI software. The relationship between signal timing and waveform was discussed based on the theory of signal integrity. The actual optimization scheme was given by combining with layout analysis. Finally, the designed DDR3 system could meet the timing requirements of JEDEC protocol through simulation iteration verification.

Key words : DDR3；SiP(system in package)；timing simulation；high density interconnection；signal integrity