Abstract： In advanced process node, as the design scale becomes larger and larger, the clock frequency becomes higher and the clock structure becomes more and more complicated, it is increasingly found that the closure of the design depends more and more on the clock quality. For complicated clock structures such as multi-input dynamic mux, IP modules with multiple internal output clocks, etc., the clock structure is analyzed, and the clock structure is extracted from the netlist based on the Innovus tool, clock spec will be updated based on these analysis. At the same time, CTS is performed on an ultra-large 16 nm top design based on the optimized clock spec, combined with the multi-tap clock tree methodology. From the results obtained, it can be found that the run time, clock latency and other aspects have been greatly improved. It can meet the requirements such as the clock length required by the project, and effectively avoid the timing conflict of the block interface.
Key words : Innovus；physical design；clock tree；multi-tap CTS
0 引言
隨著集成電路工藝進(jìn)入先進(jìn)節(jié)點(diǎn)(Advanced Node)，以及應(yīng)用場景的不斷增加，帶來芯片設(shè)計(jì)規(guī)模越來越大以及時(shí)鐘結(jié)構(gòu)更加復(fù)雜，針對時(shí)鐘結(jié)構(gòu)的分析與時(shí)鐘的實(shí)現(xiàn)也更加困難。就時(shí)鐘樹綜合(Clock Tree Synthesis，CTS)而言，時(shí)鐘結(jié)構(gòu)復(fù)雜程度的增加，可能會(huì)帶來公共路徑(Common Path)的長度減少，片上誤差(On Chip Variation，OCV)的影響增加，CTS迭代時(shí)間(Turn-Around Time)增加，以及時(shí)鐘上功耗增加等問題。因此，在物理實(shí)現(xiàn)中，CTS變得越來越重要。
