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關鍵詞: 碼分多址接入? 發射機? 誤差向量幅度? 本振源? 鎖相環
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CDMA及碼分多址接入,是一種基于擴展頻譜通信技術的多址接入方式。它采用唯一的碼字將消息信號擴展到相對更寬的頻帶上,從而減少干擾,增強系統處理能力,并且可以區分用戶。CDMA多址接入不要求分割頻率和時間,因而系統容量較高。目前國際上主流的第三代移動通信技術(WCDMA,CDMA2000以及我國提出的TD-SCDMA)都采用了CDMA技術。CDMA收發信機將成為今后通信產品的主流。
本振源作為CDMA發射機的心臟,對通信質量有著舉足輕重的影響。CDMA技術對線性度和調制精度有嚴格的要求,因此,如何根據整機指標(如:誤差向量幅度-EVM,鄰道功率抑制比-ACPR),尤其是對本振源要求較高的多模手機[1],確定本振源可實現的具體指標(相位噪聲等),并對電路進行設計與優化,成為各類CDMA通信設備設計者的新的挑戰。
本文介紹一款寬帶CDMA發射機的本振源設計過程,提供一整套針對CDMA發射機本振電路(鎖相環路)進行的電路指標確定、器件選取與參數設定以及電路設計的方案的可行性評估。
另外,對發射機系統的EVM指標進行了仿真,從而得出了合理的本振源的相位誤差指標。為便于設計者對鎖相環路的優化與仿真,筆者還編寫了一套ADS鎖相環路仿真程序,不同于常見的優化和計算在后臺進行的輔助程序。在使用本仿真程序時,設計者可以調整任意參數或器件值并迅速獲得與該調整相應的所有關鍵指標(如:相噪、雜散、穩定性)的變化。
1 原理簡介
寬帶CDMA發射機框圖如圖1所示, 其中左上部分為本振源電路。單片機通過數據總線控制鎖相環路芯片(PLL IC)使得該電路可以鎖定在不同的信道上;溫補晶振(TCXO)為鎖相環路提供精確的參考頻率源;壓控振蕩器(VCO)反饋信號與該頻率源在PLL IC內進行鑒相。鑒相輸出通過電荷泵和環路濾波器輸出到壓控振蕩器的控制端控制其輸出頻率。
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2 指標設定
與本振源相關的主要整機指標有:
·頻穩度:±2×10-6;
·EVM:15%;
·帶寬:2.5MHz;
·ACPR；-40dB/±2.5MHz。
基于上述指標,得出以下針對本振源的一些具體指標:
(1)參考頻率源頻穩度:±1.7ppm(包括溫度頻穩度、供電電壓頻穩度、負載牽引頻穩度和年老化率累加)。
(2)相位誤差； 相位誤差是由發射機的誤差向量幅度即EVM(The error vector magnitude)決定的,EVM經常被用來描述發射信號的調制精度。TD-SCDMA和WCDMA標準都用此標準來規定發射信號的的質量。EVM是對理想波形與實際波形之差的度量[2],如圖2所示[3]。
安捷倫公司提供的測量規范被廣泛應用于測量儀器和商業仿真軟件,其具體內容如下:
設Z(k)為在kT(T為符號周期)時刻通過理想接收濾波器觀測待測發射機而得到的復向量,S(k)為理想歸一化的單位圓上的參考向量。則Z(k)可以表示為[4]:
其中,W=eΔr+jΔα為頻率偏移(Δα弧度/符號)以及幅度變化率(Δr奈培(衰耗單位)/符號);C0為一恒定的復數偏移量,代表正交調制器的不平衡性;C1為一復數常量,代表發射機的任意相位和輸出功率;E(k)代表抽樣S(k)的殘差。
則誤差向量的總平方和為:
其中,C0,C1和W應使上式取得最小值,在此條件下求得每一個符號各自所對應的最小誤差向量E(k)。
EVM定義為誤差向量E(k)的幅度的均方根值,即:
其中,N=MAX-MIN+1,而MAX和MIN為EVM測量信號段的第一個符號和最后一個符號的排序數。
由以上定義可以看出:發射機的信噪比和非線性[5~7]都可能造成EVM的變化。而且這些因素對EVM的影響并不能做簡單的線性疊加。為便于通過EVM指標確定鎖相環路的具體指標,筆者利用ADS進行了系統仿真。在考慮功率放大器(PA)的非線性的前提下-設定PA增益為11.5dB,三階交調點為28.5dBm,輸入功率為10dBm,通過仿真認為將本振的EVM定為<2%是合理的。
(3)鑒相頻率:因帶寬為2.5MHz,所以鎖相環鑒相頻率亦設為2.5MHz;
(4)雜散相噪(Spur)；雜散相噪一般由鄰道功率抑制比即ACPR(Adjacent Channel Power Ratio)決定。
ACPR,有時被稱為ACLR(Adjacent Channel Leakage Ratio)。其定義為發射功率與相鄰信道上的測得功率之比。一般主要由發射機(尤其是PA)的非線性所至。但對于直接上變頻的調制方法來說,本振源在鄰道上的雜散(Spur)對該指標亦有一定的影響。
為使得該頻率點上的Spur不影響整機的ACPR(ACPR< -40dBc/±2.5MHz),設定該點上(±2.5MHz)的相噪相對幅度為-120dBc。
3 器件選取與參數確定
3.1 參考頻率源的選取
通過上述指標的確定,參考頻率源的頻率穩定度應為:±1.7ppm(包括溫度頻穩度、供電電壓頻穩度、負載牽引頻穩度和年老化率累加)。為便于確定鎖相環路的分頻比,設定其工作頻率為20MHz=8×2.5MHz(信道帶寬)。
3.2 鎖相環芯片的選取與參數設定
a. 芯片選取
芯片選取方面決定選用美國國家半導體(National Semiconductor)鎖相環芯片。本設計在EVM調制精度方面要求嚴格,它與本振源相噪之間的關系為[8]:
(4)式中,L(f)為相位噪聲密度。因此鎖相環路的相位噪聲成為設計成功與否的關鍵。首先,對鎖相環路的種類進行選擇(見表1)。
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由表1可以看出,單鎖相環整數分頻器應為首選。
為達到相噪最小化的目的,在選用鎖相環IC時,筆者著重考察了1Hz歸一化鑒相器" title="鑒相器">鑒相器噪聲的指標。理論上,該參數是在鑒相頻率為1Hz 時的鑒相器引起的相位噪聲。它是基于參考頻率源、分頻器和VCO對于帶內噪聲的貢獻一般遠小于鑒相器噪聲的實際情況而設定的一個技術指標[8]。
相位噪聲=(1Hz歸一化鑒相器噪聲)+10·log(比較頻率)+20·log(反饋支路分頻比N)
在National Semiconductor所有的單環整數分頻的鎖相環芯片中,LMX2347 的1Hz歸一化鑒相器噪聲值最低,為-220dBc/Hz, 而其他芯片一般在-210dBc 以上。計算機仿真結果表明,當1Hz歸一化鑒相器噪聲的值為-210dBc時,其相應EVM值為2.9%,而在-220dBc時為1.06%(比較頻率為2.5MHz時)。因此,選擇LMX2347成為必然。
b. 分頻比的確定
由于本項目的信道寬度為2.5MHz,因此理想的比較頻率應為2.5MHz。此時,分頻比N為1470/2.5=588, 但LMX2347僅能產生992到32767范圍內的連續分頻比,因此,決定選擇比較頻率為1.25MHz。做出該選擇的副作用是由于N值的增加,整體相噪會增加3dB。即使LMX2347的相噪特性下降3dB,其整體特性仍至少優于其他芯片-210-(-220)-3dB=7dB。而且實際仿真表明,當比較頻率為1.25MHz時,EVM為1.66%,仍舊滿足設計要求。
3.3 VCO的選取與指標設定
相位噪聲是VCO設計的關鍵指標。由公式(5)[8]求得合理的VCO在10kHz上的相噪為-95dBc/Hz。
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??? 其中,k為相位噪聲譜中帶內最低相噪密度,單位是dBc/Hz, p是帶內峰值相噪。
為減小VCO輸入電容對環路濾波器的影響,規定其輸入電容應小于10pF。
4 電路設計與仿真
為了方便電路的設計與調試,筆者編寫了一套ADS PLL仿真程序。該程序可以靈活地選擇濾波器階數,并可在每次參數變化后一次性給出與該次變化相對應的相噪、雜散、相位余量等參數,使設計者在器件值變化后可以了解PLL的整體特性。
仿真軟件以環路濾波器Z參數中的Z21代表環路增益,從而使得環路濾波器的拓撲結構可以隨便調整。另外,由于ADS軟件自身的優點,該仿真軟件可以對任何指標進行參數優化,從而得出最優的電路參量。在相位噪聲方面,該仿真程序考慮了1Hz鑒相器相噪、VCO相噪以及環路濾波器各電阻所引入的噪聲。總噪聲為各部分噪聲在PLL輸出端的疊加[8],如(6)式。
該程序給出了PLL電路的開環增益及相位變化。相位余量對應于增益為0dB時的相位變化量。考慮到本振源對ACPR參數的影響,在該仿真程序中加入了比較頻率上的雜散噪聲。
PLL IC的雜散噪聲由漏電雜散噪聲(Leakage Spur)和脈沖雜散噪聲(Pulse Spur)構成,其計算公式分別為[8]；
其中,BaseLeakageSpur為常量16dBc,LMX2347的BasePulseSpur為-322dBc,SpurGain為雜散頻點上的環路增益,Leakage為電荷泵在三態高阻下的漏電流,KΦ為鑒相增益,Fspur為雜散頻點的頻率。
為增強對雜散噪聲的抑制以提高鄰道抑制(ACPR)性能,并考慮到1.25MHz的比較頻率,本設計采用4階環路濾波器,在仿真過程中主要以雜散噪聲抑制為優化目標,優化仿真結果如圖3,其中標“□” 的線為閉環增益與相位響應,標“×”的線為開環響應。“○”線為總相位噪聲。
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(1)相位噪聲參數:根據仿真生成的相噪譜密度,求得PLL電路產生的RMS Phase error=0.95°,EVM為1.66%<2%,滿足指標要求;???????? ??????
(2)定時間:664.5μs;
(3)穩定性:相位余量32°;
(4)2.5MHz上相噪與雜散之和為-157.4,可見該本振源的雜散噪聲對2.5MHz上的ACPR影響極小。
以上方法可以廣泛應用于各種寬帶CDMA(如WCDMA、CDMA2000等)通信電路的設計。
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