中圖分類號(hào)：TN06 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.223053 中文引用格式： 徐靖林，王棟，魏斌，等. 芯片樣品驗(yàn)證平臺(tái)自適應(yīng)和同步測(cè)試功能的設(shè)計(jì)與實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用，2023，49(2)：55-60. 英文引用格式： Xu Jinglin，Wang Dong，Wei Bin，et al. Design and implementation of adaptive and synchronous test function of chip sample verification platform[J]. Application of Electronic Technique，2023，49(2)：55-60.
Design and implementation of adaptive and synchronous test function of chip sample verification platform
Xu Jinglin，Wang Dong，Wei Bin，Wang Yun，Dou Zhijun，Cheng Song
Beijing Smart-Chip Microelectronics Technology Co.， Ltd.， Beijing 100192， China
Abstract： At present, in chip design companies, sample verification is carried out for mass production chips. Most of the traditional sample verification methods design corresponding test equipment based on the characteristics of the chip, and then test the chip samples one by one through the test fixture. Different chips will design different test equipment. In this paper, an adaptive and synchronous test sample verification platform scheme is proposed, which can not only test multiple chips at the same time, but also test chips with different interfaces. It can not only test the reliability experiment, but also test other functions, which greatly saves the maintenance cost of test equipment and improves the test efficiency.
Key words : adaptive；synchronous test；sample verification；test platform
