中圖分類號： TP302.7 文獻標(biāo)識碼： A DOI：10.16157/j.issn.0258-7998.212431 中文引用格式： 寇遠博，邱澤宇，王亮，等. 基于CPU-FPGA異構(gòu)系統(tǒng)的排序算法加速[J].電子技術(shù)應(yīng)用，2022，48(1)：18-23，30. 英文引用格式： Kou Yuanbo，Qiu Zeyu，Wang Liang，et al. Sorting algorithm acceleration based on CPU-FPGA heterogeneous system[J]. Application of Electronic Technique，2022，48(1)：18-23，30.
Sorting algorithm acceleration based on CPU-FPGA heterogeneous system
Kou Yuanbo，Qiu Zeyu，Wang Liang，Huang Jianqiang
Department of Computer Technology and Applications，Qinghai University，Xining 810016，China
Abstract： Traditional sorting methods are mainly implemented in software serial mode, including bubble sorting, selective sorting and so on. These algorithms often use sequential comparison, and the operation time complexity is relatively high. In recent years, some sorting algorithms with a high degree of parallelism have been proposed, but due to the hardware characteristics of the CPU, the parallelism of these algorithms cannot be used well. And FPGA has the characteristics of good flexibility, parallelism and integration, so the advantages of these parallel algorithms can be better utilized on FPGA, thereby greatly improving the real-time performance of data sorting. Based on this, the paper designs a CPU-FPGA heterogeneous system, transplants some sorting algorithms to FPGA, and performs functional verification and theoretical performance evaluation. The results show that the system has a good acceleration effect for sorting algorithms with high parallelism, but consumes huge logic resources, and is suitable for algorithm acceleration scenarios with high real-time requirements.
Key words : FPGA；sorting algorithm；heterogeneous system；algorithm acceleration
