TI 公司的M335x系列是基于ARM Cortex-A8的微處理器,具有增強的圖像和圖形處理,外設和工業(yè)接口如EtherCAT和PROFIBUS,支持Linux®和Android高級操作系統(tǒng)(HLOS),包括用于3D加速的POWERVR SGX™圖像加速器,主要用在游戲機外設, 家庭和工業(yè)自動化,智能銷售系統(tǒng),打印機,高擋玩具,消費類醫(yī)療設備和衡器.本文介紹了AM335x系列產品主要特性和框圖,以及AM335x評估板TMDSSK3358主要特性,框圖,電路圖和材料清單.

The AM335x microprocessors, based on the ARM Cortex-A8, are enhanced with image, graphics　processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS.

The device supports the following high-level operating systems (HLOSs) that are available free of charge from TI:

• Linux®
• Android™

The AM335x microprocessor contains these subsystems:

• Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor.
• POWERVR SGX™ Graphics Accelerator subsystem for 3D graphics acceleration to support display and gaming effects.
• The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility.

The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT,PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others.

AM335x 主要特性:

Highlights
Up to 1-GHz ARM Cortex-A8 32-Bit RISC Microprocessor
NEON SIMD Coprocessor
32KB of L1 Instruction and 32KB Data Cache with Single-Error Detection (parity)
256KB of L2 Cache with Error Correcting Code (ECC)
mDDR(LPDDR), DDR2, DDR3, DDR3L Support
General-Purpose Memory Support (NAND, NOR, SRAM) Supporting Up to 16-bit ECC
SGX530 3D Graphics Engine
LCD and Touchscreen Controller
Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
Real-Time Clock (RTC)
Up to Two USB 2.0 High-Speed OTG Ports with Integrated PHY
10, 100, 1000 Ethernet Switch Supporting Up to Two Ports
Serial Interfaces Including:
Two Controller Area Network Ports (CAN)
Six UARTs, Two McASPs, Two McSPI, and Three I2C Ports
12-Bit Successive Approximation Register (SAR) ADC
Up to Three 32-Bit Enhanced Capture Modules (eCAP)
Up to Three Enhanced High-Resolution PWM Modules (eHRPWM)
Crypto Hardware Accelerators (AES, SHA, PKA, RNG)
MPU Subsystem
Up to 1-GHz ARM^® Cortex™-A8 32-Bit RISC Microprocessor
NEON™ SIMD Coprocessor
32KB of L1 Instruction Cache with Single-Error Detection (parity)
32KB of L1 Data Cache with Single Error-Detection (parity)
256KB of L2 Cache with Error Correcting Code (ECC)
176KB of On-Chip Boot ROM
64KB of Dedicated RAM
Emulation and Debug
JTAG
Interrupt Controller (up to 128 interrupt requests)
On-Chip Memory (Shared L3 RAM)
64 KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
Accessible to all Masters
Supports Retention for Fast Wake-Up
External Memory Interfaces (EMIF)
mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
mDDR: 200-MHz Clock (400-MHz Data Rate)
DDR2: 266-MHz Clock (532-MHz Data Rate)
DDR3: 400-MHz Clock (800-MHz Data Rate)
DDR3L: 400-MHz Clock (800-MHz Data Rate)
16-Bit Data Bus
1 GB of Total Addressable Space
Supports One x16 or Two x8 Memory Device Configurations
General-Purpose Memory Controller (GPMC)
Flexible 8-Bit and 16-Bit Asynchronous Memory Interface with Up to seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
Uses BCH Code to Support 4-Bit, 8-Bit, or 16-Bit ECC
Uses Hamming Code to Support 1-Bit ECC
Error Locator Module (ELM)
Used in Conjunction with the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
Supports 4-Bit, 8-Bit, and
16-Bit per 512-byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
Supports protocols such as EtherCAT, PROFIBUS, PROFINET, EtherNet/IP™, and more
Peripherals Inside the PRU-ICSS
One UART Port with Flow Control Pins, Supports Up to 12 Mbps
Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
One MDIO Port
One Enhanced Capture (eCAP) Module
Power Reset and Clock Management (PRCM) Module
Controls the entry and Exit of Stand-By and Deep-Sleep Modes
Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing and Power Domain Switch-On Sequencing
Clocks
Integrated 15-35 MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
Power
Two Non-Switchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKE-UP])
Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
Implements SmartReflex Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation and Performance (Adaptive Voltage Scaling [AVS])
Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
Independent Power-on-Reset (RTC_PWRONRSTn) Input
Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wake Up) or Cortex-A8 (for Event Notification)
Programmable Alarm Can be Used with External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
Up to Two USB 2.0 High-Speed OTG Ports with Integrated PHY
Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
Integrated Switch
Each MAC Supports MII, RMII, RGMII and MDIO Interfaces
Ethernet MACs and Switch Can Operate Independent of Other Functions
IEEE 1588v2 Precision Time Protocol (PTP)
Up to Two Controller-Area Network (CAN) Ports
Supports CAN Version 2 Parts A and B
Up to Two Multichannel Audio Serial Ports (McASP)
Transmit and Receive Clocks Up to 50 MHz
Up to Four Serial Data Pins per McASP Port with Independent TX and RX Clocks
Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and similar Formats
Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
FIFO Buffers for Transmit and Receive (256 bytes)
Up to Six UARTs
All UARTs Support IrDA and CIR Modes
All UARTs Support RTS and CTS Flow Control
UART1 Supports Full Modem control
Up to Two Master and Slave McSPI Serial Interfaces
Up to Two Chip Selects
Up to 48 MHz
Up to Three MMC, SD, and SDIO Ports
1-Bit, 4-Bit and 8-Bit MMC, SD, and SDIO Modes
MMCSD0 has dedicated Power Rail for 1.8-V or 3.3-V Operation
Up to 48-MHz Data Transfer Rate
Supports Card Detect and Write Protect
Complies with MMC4.3 and SD and SDIO 2.0 Specifications
Up to Three I2C Master and Slave Interfaces
Standard Mode (up to 100 kHz)
Fast Mode (up to 400 kHz)
Up to Four Banks of General-Purpose IO (GPIO)32 GPIOs per Bank (Multiplexed with Other Functional Pins) GPIOs Can be Used as Interrupt Inputs (Up to Two Interrupt Inputs per Bank)
Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs
Eight 32-Bit General-Purpose Timers
DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
DMTIMER4 - DMTIMER7 are Pinned Out
One Watchdog Timer
SGX530 3D Graphics Engine
Tile-Based Architecture Delivering Up to 20 Million Polygons per second
Universal Scalable Shader Engine is a Multi-Threaded Engine Incorporating Pixel and Vertex Shader Functionality
Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0 and OGL2.0
Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0, and OpenMax
Fine-Grained Task Switching, Load Balancing and Power Management
Advanced Geometry DMA Driven Operation for Minimum CPU Interaction
Programmable High-Quality Image Anti-Aliasing
Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
LCD Controller
Up to 24-Bits Data Output; 8-Bits per Pixel (RGB)
Resolution Up to 2048x2048 (With Maximum 126-MHz Pixel Clock)
Integrated LCD Interface Display Driver (LIDD) Controller
Integrated Raster Controller
Integrated DMA Engine to Pull Data from the External Frame Buffer without Burdening the Processor via Interrupts or a Firmware Timer
512-Word Deep Internal FIFO
Supported Display Types:
Character Displays - Uses LCD Interface Display Driver (LIDD) Controller to Program these Displays
Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
12-Bit Successive Approximation Register (SAR) ADC
200K Samples per Second
Input Can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 analog Switch
Can be Configured to Operate as a 4-wire, 5-wire, or 8-wire Resistive Touch Screen Controller (TSC) Interface
Up to Three 32-Bit Enhanced Capture Modules (eCAP)
Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
Up to Three Enhanced High-Resolution PWM Modules (eHRPWM)
Dedicated 16-Bit Time-Base Counter with Time and Frequency Controls
Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
Device Identification
Contains Electrical fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
Production ID
Device Part Number (Unique JTAG ID)
Device Revision (readable by Host ARM)
Debug Interface Support
JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
Supports Device Boundary Scan
Supports IEEE 1500
DMA
On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTC) and One Third-Party Channel Controller (TPCC), Which Supports Up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
Transfers to and from On-Chip Memories
Transfers to and from External Storage (EMIF, General-Purpose Memory Controller, Slave Peripherals)
Inter-Processor Communication (IPC)
Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A8, PRCM, and PRU-ICSS
Mailbox Registers that Generate Interrupts
Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
Spinlock has 128 Software-Assigned Lock Registers
Security
Crypto Hardware Accelerators (AES, SHA, PKA, RNG)
Boot Modes
Boot Mode is Selected via Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Packages:
298-Pin S-PBGA-N298 Via Channel™ package
(ZCE Suffix), 0.65-mm Ball Pitch
324-Pin S-PBGA-N324 package
(ZCZ Suffix), 0.80-mm Ball Pitch

AM335x應用:

• Gaming Peripherals
• Connected Vending Machines
• Home and Industrial Automation
• Weighing Scales
• Consumer Medical Appliances
• Educational Consoles
• Printers
• Advanced Toys
• Smart Toll Systems

圖1.AM335x功能框圖

AM335x評估板TMDSSK3358

The AM335x Starter Kit (TMDSSK3358) can be used as an evaluation and development platform for low cost AM335x based solutions and networking platforms. The embedded emulation logic allows emulation and debug using standard development tools such as TI’s Code Composer Studio by just using the supplied USB cable. It is not intended for use in end products. All of the design information is freely available and can be used as the basis for the development of an AM335x based product.

TMDSSK3358 is partitioned into two different boards: the main board (processor, peripherals & the main power supply) and the LCD Carrier board (LCD and touch screen). The TMDSSK3358 main board and the LCD carrier board mounted are mounted together using 10mm standoffs. The TMDSSK3358 main board has dimensions of 5.257” x 2.798 “and that of the LCD Carrier board is 4.963” x 2.798 “.

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圖4. 評估板TMDSSK3358系統(tǒng)外形圖

圖5. 評估板TMDSSK3358框圖

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